Internally Compensated LDO Regulators for Modern System-on-Chip Design by José María Hinojo Clara Luján Martínez & Antonio Torralba

Author:José María Hinojo , Clara Luján Martínez & Antonio Torralba
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

Transistor

Size [m/m]

M

2000.0/0.06

M

2.7/0.27

M

0.54/0.27

M

6.51/0.27

M

7.53/0.27

M

8.1/0.27

Component

Value

R

200 [k]

R

300 [k]

R

300 [k]

I

2.5 [A]

C

100 [pF]

C

18.48 [pF]

3.5.1 Stability Analysis

In Sect. 3.4, a methodology for the design of the proposed compensation network was described, which is based on the determination of a critical I. A stability analysis of the designed LDO regulator is performed in this section. Figure 3.13 depicts its small-signal model, where g and g are the transconductance of the first and the second stages of the error amplifier, respectively. The output resistance of the first stage is represented by R and C models the parasitic capacitance at the gate of transistor M in Fig. 3.12. It is important to highlight that the replica circuit that controls the gate voltage of M is not in the signal path and, consequently, the whole compensation scheme can be modelled as a passive network composed of three single resistors, R, R and R, and the capacitor, C.

Fig. 3.13Small-signal model of the proposed IC-LDO regulator

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